Solution of small spacing LED display chip side

　　LED display size reduces chip size to shrink.

　　On the surface, it is the problem of layout design. It seems that as long as you design a smaller layout according to your needs, you can solve it. But can the chip size shrink down unlimited? the answer is negative. As follows, the following reasons restricted the degree of chip size shrinking:

　　(1) Limit the LED display packaging processing. During the packaging process, the two factors limit the reduction of chip size. The first is the restriction of the mouth. The solid crystals need to absorb the chip. The short side size of the chip must be greater than the inner diameter of the mouth suction. At present, the inner diameter of cost -effective mouth suction is about 80um. The second is the limitation of the welding line. The first is that the welding line disk, that is, the chip electrode, must be large enough, otherwise the reliability of the welding line cannot be guaranteed. Secondly, the distance between the electrodes must be large enough, otherwise the two welding lines will inevitably interfere with each other.

　　(2) Restriction of LED display chip processing. There are also two restrictions during chip processing. One is the restrictions of the layout layout. In addition to the limitations of the above -mentioned seal end, the electrode size, the electrode spacing is required, the electrode and MESA distance, the width of the trail, and the boundary line spacing of different layers have its restrictions. Determine the scope of specific restrictions. Generally, the minimum distance from the P electrode to the edge of the chip will be limited to above 14 μm.

　　The second is the limitation of the LED display griming processing capacity. SD paddles+mechanical cracks have limits, and the chip size may not be cracking. When the diameter of the wafers increases from 2 inches to 4 inches, or in the future to 6 inches, the difficulty of paddling is increased, that is, the size of the processable chip will increase. Taking 4 inches as an example, if the length of the chip is less than 90 μm and the length ratio is greater than 1.5: 1, the loss of yield will increase significantly.

　　For the above reasons, the author boldly predicts that after the chip size is reduced to 17mil2, the chip design and process processing capacity is close to the limit, and there is basically no reduction of space, unless the chip technology solution has a big breakthrough.

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